Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise ... Motorola Communications Device Data, Data ...
IEEE

A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector

Abstract: This article presents an analog delay-locked loop (DLL) designed for high-precision measurement applications, featuring low static phase offset (SPO) and fast locking speed, such as ...