IEEE

Pipelined Implementation of Secure Hash Algorithm on FPGA for Enhanced Performance

Abstract: This paper presents the implementation and opti-mization of the SHA-256 algorithm on an FPGA platform, specif-ically on the Xilinx Artix-4 DDR board. The main objective is to enhance the ...
IEEE

Quantum Circuit Optimization Techniques Using Iterative Pre-Conditioned Gradient Descent

Abstract: This paper introduces new optimization techniques which are optimizing QFT(Qunatum Fourier Transformation) circuit, Momentum-Based Iterative Pre-Conditioned Gradient Descent and Nesterov ...