IEEE

Implementation of 256-Bit AES and SHA3 on FPGA

Abstract: The work discusses an implementation of the SHA3 algorithm and AES encryption/decryption algorithms which is of 256 bits using Verilog HDL on FPGA. The approach emphasizes optimizing ...
IEEE

Design and Implementation of a Data Encryption Framework Simulink Model for Protecting ...

Abstract: Internet-of-Medical-Things (IoMT) based sensitive data protection has become a critical problem lately. IoMT-sensitive data are used to connect patients with adults. Since every record, data ...